System for, and method of, etching a surface on a wafer

ABSTRACT

First and second electrodes at opposite ends and magnets between the electrodes define an enclosure. Inert gas (e.g. argon) molecules pass into the enclosure through an opening near the first electrode and from the enclosure through an opening near the second electrode. A ring near the first electrode, a plate near the second electrode and the magnets are at a reference potential (e.g. ground). The first electrode is biased at a high voltage by a high alternating voltage to produce a high intensity negative electrical field. The second electrode is biased at a low negative voltage by a low alternating voltage to produce a low intensity negative electrical field. Electrons movable in a helical path in the enclosure near the first electrode ionize inert gas molecules. A wafer having a floating potential and an insulating layer is closely spaced from the second electrode. The electrode and the wafer define plates of a first capacitor having a dielectric formed by inert gas molecules and ions between the plates to provide a high impedance. The wafer and the inert gas ions in the enclosure define opposite plates of a second capacitor, in series with the first capacitor, having the insulating layer as the dielectric to define a low impedance. The first capacitor accordingly controls and limits the speed at which the gas ions move to the insulating layer surface to etch this surface. The resultant etch, only a relatively few Ångstroms, of the insulating layer is smooth, uniform and accurate even in sockets as for vias.

[0001] This invention relates to apparatus for, and methods of, etchinga surface of a wafer to provide a fresh and clean surface for providinga deposition on the surface. More particularly, the invention relates toapparatus for, and methods of, etching a surface of an insulating layerin a wafer, and etching walls defining a socket in the wafer, so thatthe etchings of the surface of the insulating layer, and the etching ofthe surfaces of the walls in the socket, are smooth and uniform and sothat the surfaces do not have any pits.

BACKGROUND OF THE INVENTION

[0002] Integrated circuit chips are being used now in all kinds ofapparatus to provide complex electrical circuitry for controllingdifferent operations or for providing data and mathematical calculationsin business, education, science and many other fields. With successiveadvances in time, the size of the integrated circuit chips hasprogressively decreased, particularly because the thickness of theelectrical leads in the chips has progressively decreased. Even as thechips have decreased in size, the circuitry on the chips has becomeprogressively complex.

[0003] The integrated chips are formed in wafers, each of which holds anumber, hundreds and often even thousands, of integrated circuit chips.The chips on the wafer are formed from a plurality of successive layers.Some of the layers provide electrical insulation. Others of the layersare electrically conductive. Electrical pegs or vias are providedbetween the different electrically conductive layers. The electricalpegs or vias are disposed in sockets provided in insulating layers inthe chips. When the fabrication of the wafers has been completed, eachchip defines electrical circuitry which performs specialized, oftencomplex, operations.

[0004] The fabrication of the different layers in an integrated circuitchip has to be precise. For example, the width and thickness of thecircuit leads in the different layers have to be precise in order tomaintain the proper impedance values for different components in thecircuits. If the proper impedance values are not maintained, theoperation of the circuitry in the integrated circuit chip is impaired.Variations in the width and thickness of the circuit leads can resultfrom impurities in the surfaces of different layers in the chips andfrom uneven and non-smooth surfaces on the insulating layers on whichelectrically conductive material is deposited. The criticality inmaintaining surfaces even and smooth has increased as the thickness ofthe leads on the integrated circuit chips has decreased.

[0005] Apparatus has existed for a considerable number of years to etchthe surfaces of different layers on the chips. The purpose of theetching has been to clean and refresh the surfaces to receive subsequentlayers of deposition. The etching has produced uneven surfaces on thelayers, thereby producing variations in the characteristics of theelectrical material subsequently deposited on the uneven surfaces. Theproblem has been aggravated as the thickness of the layers hasdecreased. Attempts have been made to resolve this problem by making theetched surfaces even and uniform. The attempts have provided significantsuccess but improvements in the smoothness and evenness of the surfacesof the insulating layer are constantly desired.

BRIEF DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0006] First and second electrodes at opposite ends and magnets betweenthe electrodes define an enclosure. Inert gas (e.g. argon) moleculespass into the enclosure through an opening near the first electrode andfrom the enclosure through an opening near the second electrode. A ringnear the first electrode, a plate near the second electrode and themagnets are at a reference potential (e.g. ground).

[0007] The first electrode is biased at a high negative voltage by ahigh alternating voltage to produce a high intensity electrical field.The second electrode is biased at a low negative voltage by a lowalternating voltage to produce a low intensity electrical field.Electrons movable in a helical path in the enclosure near the firstelectrode ionize inert gas molecules.

[0008] A wafer having a floating potential and having an insulatinglayer is closely spaced from the second electrode. The electrode and thewafer define plates of a first capacitor having a dielectric formed byinert gas molecules and ions between the plates to provide a highimpedance. The wafer and the gas ions in the enclosure define oppositeplates of a second capacitor, in series with the first capacitor, havingthe insulating layer as the dielectric to define a low impedance.

[0009] The first capacitor accordingly controls and limits the speed atwhich the gas ions move to the insulating layer surface to etch thissurface. The resultant etch, only of a relatively few Ångstroms, of theinsulating layer is smooth, uniform and accurate even in holes as forvias and does not have any pits.

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings:

[0011]FIG. 1 is a schematic elevational view of apparatus constituting apreferred embodiment of the invention for etching a surface of aninsulating layer in a wafer to produce an even and uniform surface,without any pits on the insulating layer;

[0012]FIG. 2 is an enlarged fragmentary simplified schematic elevationalview of the construction of a wafer, and;

[0013]FIG. 3 is an enlarged schematic elevational view of electricalfields produced in an enclosure by the apparatus shown in FIG. 1, thewafer being disposed in the enclosure;

[0014]FIG. 4a is an enlarged fragmentary elevational schematic viewshowing the disposition of particular ones of the components in thepreferred embodiment of FIG. 1;

[0015]FIG. 4b is an enlarged fragmentary schematic circuit diagramshowing the electrical equivalent of the components in FIG. 4a as a pairof capacitors in series, one of the capacitors having a high impedanceand the other capacitor having a low impedance;

[0016]FIG. 5a is an enlarged fragmentary schematic elevational viewshowing the disposition in the prior art of the particular ones of thecomponents shown in FIG. 4a; and

[0017]FIG. 5b is an enlarged fragmentary schematic circuit diagramshowing the electrical equivalent of the disposition of the prior artcomponents in FIG. 5a as a single capacitor having a low impedance.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION

[0018] FIGS. 1-4 show a preferred embodiment, generally indicated at 10,of apparatus for etching a surface 12 of an insulating layer 14 in awafer generally indicated at 16. As will be appreciated, the wafer maybe formed from a plurality of stacked layers, some of them electricallyconductive and others electrically insulating. In addition to theinsulating layer 14, an electrically conductive layer 15 and anelectrically insulating base layer 17 are schematically shown torepresent the different layers in the integrated circuit chip. Theinsulating layer 14 may have a plurality of a grooves or sockets 18. Theinsulating layer 14 may illustratively be made from a suitable materialsuch as a polyamide.

[0019] The insulating layer 14 may illustratively have a thickness ofapproximately three (3) microns. The sockets 18 may be completely, orpartially, formed through the thickness of approximately three (3)microns in the insulating layer 14. FIG. 2 illustratively shows thesockets 18 as extending completely through the thickness of theinsulating layer 14. The preferred apparatus 10 of this inventionillustratively may etch approximately one hundred angstroms (100 Å) fromthe surface 12 of the insulating layers 14 in a smooth and even layerand without any pits in the layer.

[0020] The apparatus 10 includes an enclosure 20 which may be formed inpart by an electrode 22, an electrode 24 displaced from, but preferablysubstantially parallel to, the electrode 22 and magnets 26 and 28disposed in a transverse (preferably substantially perpendicular)relationship to the electrodes 22 and 24. The electrode 22 is disposedin a contiguous and substantially parallel relationship to the wafer 16and is movable in position toward or away from the wafer, as indicatedby a double-headed arrow 25. The spacing between the wafer 16 and theelectrode 22 may illustratively be in the order of 0.1-2 mm. A plate 30extending from the magnet 26 in a substantially parallel, but spaced,relationship to the electrode 22 also defines the enclosure 20. A ring32 extending from the magnet 28 to a position spaced from, butcontiguous to, the electrode 24 also defines in part the enclosure 20.

[0021] The magnets 26 and 28 preferably constitute permanent magnets butthey may also constitute magnetizable members on which windings aredisposed to produce a saturable magnetic flux when a current flowsthrough the windings. The magnets 26 and 28 may have a northpolarization (indicated by the letter “N” in FIG. 1) at their positionsof contiguity and may have a south polarization (indicated by the letter“S” in FIG. 1) at their opposite ends. The magnets 26 and 28, the plate30 and the ring 32 are provided with a reference potential such as aground 34. The wafer 16 is disposed in close proximity to the electrode22 within the enclosure 20 and in substantially parallel relationship tothe electrode. The wafer 16 is at a floating potential.

[0022] The electrode 22 receives a relatively low AC voltage from apower supply 36 at a suitable frequency such as approximately 13.56 MHz.As will be explained in detail subsequently, this causes the electrode22 to receive a relatively low negative DC bias such as a negative biasin the order of −100 volts to −500 volts. A matching network 38 ispreferably disposed electrically between the power supply 36 and theelectrode 22 to match the impedance of the power supply to the impedanceof the electrode.

[0023] The electrode 24 receives a relatively high AC voltage from apower supply 40 at a suitable frequency such as approximately 13.56 MHz.As will be explained in detail subsequently, this causes the electrode24 to have a relatively high negative DC bias such as a negative bias inthe order of −1000 volts to −3000 volts. A matching network and zerobias circuit 42 are preferably disposed electrically between the powersupply 40 and the electrode 24 to match the impedance of the powersupply to the impedance of the electrode and to provide substantially aground potential on the electrode. The zero bias circuit may constitutean inductance between the electrode 24 and ground to provide a highimpedance for alternating voltages and to provide a low impedance for aDC voltage. The power supplies 36 and 40 may constitute a single powersupply.

[0024] A conduit 44 is provided for introducing molecules of an inertgas such as argon into the enclosure 20 from a source 45. The argonmolecules pass into the enclosure 30 through the space between theelectrode 24 and the ring 32. The argon molecules pass out of theenclosure 30 through the space between the plate 34 and the wafer 16.The argon gas flow through the enclosure 30 may illustratively be at aflow rate of 0.1-50 SCCM at a working pressure of 0.5-5 mTorr. Themovement of the argon molecules through the enclosure 20 is facilitatedby a vacuum pump 47.

[0025] A negative bias is produced on the electrode 22 because of thealternating voltage applied to the electrode. In the positive halfcycles of the alternating voltage, the electrode 22 attracts electronsbecause of the electrical field between the electrode and the groundpotential 34 on the plate 30. In the negative half cycles of thealternating voltage, positive ions are attracted to the electrodebecause of the electrical field between the electrode and the groundpotential 34 on the plate 30. Since the electrons are considerablylighter in weight than the positive ions, they move faster toward theelectrode 22 than the positive ions. This causes the electrons toaccumulate in the space adjacent the electrode 22, thereby producing thenegative DC bias on the electrode. The electrode 24 receives a negativebias because of the same physical phenomenon. However, the negative biason the electrode 22 is considerably less than the negative DC bias onthe electrode 24 because of the differences in the voltages applied tothe electrodes.

[0026] As previously indicated, the magnetic field produced by themagnets 26 and 28 is substantially perpendicular to the electricalfields produced by the electrodes 22 and 24. This causes electrons inthe enclosure 20 to move in a spiral or helical path between theelectrode 22 and the plate 30, and between the electrode 24 and the ring32, because of the ground potentials on the plate and the ring. Theelectrons strike molecules of argon gas and ionize these molecules.Since the electrical field between the electrode 24 and the ring 32 isconsiderably stronger than the electrical field between the electrode 22and the plate 30, most of the ionization of argon molecules occurs inthe region of the electrode 24. Some of these argon ions then move intothe region of the electrode 22.

[0027]FIG. 3 illustrates at 46 lines of force produced by the electricalfield between the electrode 22 and the plate 30. Arrows indicate thedirection of the lines 46 of force. The electrons in the enclosure 20travel in a spiral or helical path along the force lines 46, the spiralor helical path resulting from the force of the magnetic field as theelectrons move along the force lines 46. In like manner, FIG. 3illustrates at 48 lines of force produced by the electrical fieldbetween the electrode 24 and the ring 32 and between the electrode andthe grounded magnets 26 and 28. The electrons in the enclosure 20 travelin a spiral or helical path along the force lines 48 because of theforce on the electrons by the magnets 26 and 28.

[0028] Applicant's assignee of record in this application has previouslysold one (1) unit of apparatus with features similar to the apparatusshown in FIG. 1. This unit may have been sold more than one (1) yearprior to the date of this application. However, there is one significantdifference between the apparatus 10 constituting the preferredembodiment of the invention and the unit previously sold by applicant'sassignee. The significant difference is that the wafer 16 engaged theelectrode 22 in the one (1) unit sold prior to the date of thisapplication. The circuit equivalent of this arrangement is shown in FIG.5b and is indicated as prior art in that Figure. As previouslyindicated, the wafer 16 is separated from the electrode 22 in thepreferred embodiment 10 of this invention.

[0029] As will be seen, the combination of the electrode 22 and thewafer 16 in FIG. 5a is seen as a single electrode or plate in acapacitor 50 in FIG. 5b. The other electrode or plate in the capacitor50 is defined by the positive ions in the enclosure 20 at positionsadjacent the electrode 24. These positive ions are schematicallyillustrated by dots (.) at 51 in FIG. 3. The dielectric between theplates of the capacitor 50 may be considered to be the insulating layer14. The impedance of the capacitor 50 is accordingly relatively lowbecause the insulting layer 14 is relatively thin and because thedielectric constant of the insulating layer is lower than the dielectricconstant of air or the dielectric constant of a vacuum.

[0030] Since the impedance of the capacitor 50 is relatively low, arelatively large current flows through the capacitor. This currentresults from the attraction of the argon ions to the insulating layer 14because of the negative DC voltage on the electrode 22. The relativelylarge current produces an etching of molecules and ions from the surface12 of the insulating layer 14. This etching is of such a force that theetching is not smooth, even or uniform. Pitting of the surface of theinsulating layer 14 accordingly occurs. The problem is particularlyaggravated in considering the etching of the walls of the sockets 18 inthe insulating layer 14.

[0031] Since the etching does not result in a smooth, even and uniformsurface 12 of the insulating layer 14, any subsequent deposition of anelectrically conductive layer on the surface 12 has significantdifferences in thickness of the electrically conductive material atdifferent positions on the surface 12. This significantly affects theelectrical characteristics of the electrical deposition on theinsulating layer 14 and produces significant deterioration in theperformance characteristics of the integrated circuit chips formed fromthe wafer.

[0032] As previously indicated, the wafer 16 is separated from theelectrode 22 in the preferred embodiment 10 of this invention. Theseparation may be in the order of 0.1 to 2.0 millimeters, This causestwo (2) capacitors 52 and 54 in FIG. 4b to be defined by the electrode22, the wafer 16 and the charge produced by the argon ions 51 in theenclosure 20 in the vicinity of the electrode 22. The plates of thecapacitor 52 in FIG. 4b may be respectively considered to be defined bythe electrode 22 and by the electrically conductive deposition layers inthe wafer 16. Although there may be argon ions in this gap, the argonions are relatively small in number. Furthermore, the gap is so smallthat the argon ions cannot be accelerated to any significant degree.Because of these factors, the dielectric in the capacitor 52 in FIG. 4bmay be considered to be the gap between the electrode 22 and the wafer16. This gap causes the impedance of the capacitor 52 to be relativelyhigh. This impedance can be adjusted to any desired value by adjustingthe position of the electrode 22 in the opposite directions 25 to varythe distance between the electrode and the wafer 16.

[0033] The capacitors 52 and 54 may be considered to be in series asshown in FIG. 4b. The capacitor 54 may be considered to have platesdefined by the electrically conductive layers in the wafer 16 and by thecharge provided by the argon ions 51 in the enclosure 20 in the vicinityof the electrode 20. The dielectric for the capacitor 54 may beconsidered to be the insulating layer 14. The impedance of the capacitor54 is relatively low, particularly in relation to the impedance of thecapacitor 52, because of the thin dimension of the insulating layer 14and the dielectric constant of the insulating layer.

[0034] The current through the series circuit including the capacitors52 and 54 in FIG. 4b is limited and controlled by the capacitor 52because of the high impedance of the capacitor. This limited andcontrolled current provides a gentle etching of the surface 12 of theinsulating layer 14 and of the walls of the sockets 18. As a result, anyspecified amount of material may be etched from the surface 12 of theinsulating layer 14 and from the walls of the sockets 18. For example,an etching of the material of the insulating layers 14 and the walls ofthe sockets 18 may be provided in a thickness of approximately onehundred Ångstroms (100 Å).

[0035] The etching produces smooth, even and uniform surfaces of theinsulating layer 14 by the apparatus 10 as a result of the etching. Thisprovides for a deposition of a smooth, uniform and even thickness of anelectrically conductive material on the etched surface of the insulatinglayer 14. The etching of the walls in the sockets 18 is also even,uniform and smooth. This constitutes a distinct advance over the priorart, even the prior art as represented by the single unit of theapparatus sold by applicant's assignee prior to the filing date of thisapplication, this prior unit being shown in FIG. 5a and beingrepresented by the electrical circuitry shown in FIG. 5b.

[0036] As shown schematically in FIG. 4a, balls 60 made from a suitablematerial such as copper may be provided on the electrically conductivesurface of the wafer 160. The balls 60 operate as electrical leads. Theballs 60 are known in wafers of the prior art. The balls 60 are notaffected by the actions of the capacitances 52 and 54 in FIG. 4b.

[0037] Although the invention has been disclosed and illustrated withrelation to particular embodiments, the principles involved are capableof being used in numerous other embodiments which will be apparent topersons of ordinary skill in the art. The invention is, therefore, to belimited only as indicated by the scope of the appended claims.

What is claimed is:
 1. In combination for etching an insulating layer ina wafer to present a clean and fresh surface on the insulating layer fordeposition, a conduit for molecules of an inert gas, a first electrodebiased to a first voltage and spaced from the wafer, a second electrodebiased to a second voltage lower than the first voltage and spaced fromthe first electrode and the wafer, magnetic members providing a magneticfield, the first electrode and the magnetic members being disposedrelative to each other and to the molecules of the inert gas forionizing the molecules of the inert gas, and the second electrode andthe wafer being disposed relative to each other and to the ions of theinert gas to obtain a movement of the ions to the wafer at a low andcontrolled speed for an etching of the surface of the insulating layerby the ions at the low and controlled speed.
 2. In a combination as setforth in claim 1, a first member disposed adjacent the first electrodefor providing a reference potential different from the bias on the firstelectrode to create a first electrical field, and a second memberdisposed adjacent the second electrode for providing the referencepotential to create a second electrical field, the first electricalfield and the magnetic field being disposed relative to each other andto the molecules of the inert gas from the supply for ionizing themolecules of the inert gas, the second electrical field and the magneticfield being disposed relative to each other and to the ions of the inertgas to obtain the movement of the ions to the wafer at the low andcontrolled speed.
 3. In a combination as set forth in claim 1, a firstsource of alternating voltage for creating the bias on the firstelectrode, the bias on the first electrode being a negative directvoltage, a second source of alternating voltage for creating the bias onthe second electrode, the bias on the second electrode being a negativedirect voltage.
 4. In a combination as set forth in claim 1, the firstelectrode being disposed in a substantially parallel and contiguousrelationship to the wafer, there being a path for the flow of the argonmolecules from the vicinity of the first and second electrodes and themagnetic members.
 5. In a combination as set forth in claim 1, the waferbeing at a floating potential, there being first and second electricallyconductive members respectfully adjacent the first and second electrodesat a reference potential to provide for the creation of electricalfields respectively between the first electrode and the firstelectrically conductive member and between the second electrode and thesecond electrically conductive member.
 6. In a combination as recited inclaim 2, a first source of alternating voltage for creating the bias onthe first electrode, the bias on the first electrode being a negativedirect voltage, a second source of alternating voltage for creating thebias on the second electrode, the bias on the second electrode being anegative direct voltage, the first electrode being disposed in asubstantially parallel and contiguous relationship to the wafer, therebeing a path for the flow of the argon molecules from the vicinity ofthe first and second electrodes and the magnetic members, the waferbeing at a floating potential, there being first and second electricallyconductive members respectfully adjacent the first and second electrodesat a reference potential to provide for the creation of electricalfields respectively between the first electrode and the firstelectrically conductive member and between the second electrode and thesecond electrically conductive member.
 7. In combination for etching aninsulating layer in a wafer to present a clean and fresh surface on theinsulating layer for deposition, an enclosure defined by magneticmembers forming a magnetic field and by first and second electrodesspaced from each other and from the wafers and providing electricalfields, a supply of molecules of an inert gas for introducing themolecules into the enclosure, a first source of an alternating voltagefor producing a direct negative voltage of a high magnitude on the firstelectrode for the creation of a first electrical field of a highmagnitude in the enclosure, a second source of an alternating voltagefor producing a direct negative voltage of a low magnitude on the secondelectrode for the creation of a second electrical field of a lowmagnitude in the enclosure, the molecules of the inert gas in theenclosure being ionized by the combination of the electrical andmagnetic fields, and the wafer being disposed relative to the secondelectrode and relative to the argon ions in the enclosure to receive anetching of a low magnitude on the surface of the insulating layer by theargon ions in the enclosure.
 8. In a combination as set forth in claim7, an opening in the enclosure for the flow of the molecules and ions ofthe inert gas from the enclosure, the first source of the alternatingvoltage being operative to produce a direct voltage of the highmagnitude and a negative polarity at the first electrode, the secondsource of the alternating voltage being operative to produce a directvoltage of the low magnitude and a negative polarity at the secondelectrode.
 9. In a combination as set forth in claim 7, a firstelectrical conductor disposed in adjacent relationship to the firstelectrode at a particular reference potential to produce a firstelectrical field between the first electrode and the first electricalconductor, and a second electrical conductor disposed in adjacentrelationship to the second electrode at the particular referencepotential to produce a second electrical field between the secondelectrode and the second conductor.
 10. In a combination as set forth inclaim 7, the wafer being disposed between the first and secondelectrodes in a substantially parallel relationship to the first andsecond electrodes and closer to the second electrode than the firstelectrode, the wafer being at a floating potential relative to thenegative potentials on the first and second electrodes and relative tothe reference potential.
 11. In a combination as set forth in claim 7,the wafer being disposed in a spaced, but contiguous, relationship tothe second electrode to create a first capacitor between the secondelectrode and the wafer and to create a second capacitor between thewafer and the ions of the inert gas in the enclosure.
 12. In acombination as set forth in claim 10, a vacuum pump for producing avacuum in the enclosure, there being a space between the secondelectrode and the second conductive member for the flow of the moleculesand ions of the inert gas from the enclosure.
 13. In a combination asset forth in claim 10, a first electrical conductor disposed in adjacentrelationship to the first electrode at a particular reference potentialto produce a first electrical field between the first electrode and thefirst electrical conductor, a second electrical conductor disposed inadjacent relationship to the second electrode at the particularreference potential to produce a second electrical field between thesecond electrode and the second conductor. the wafer being disposed in aspaced, but contiguous, relationship to the second electrode to create afirst capacitor between the second electrode and the wafer and to createa second capacitor between the wafer and the ions of the inert gas inthe enclosure.
 14. In combination for etching an insulating layer in awafer disposed in an enclosure to present a clean and fresh surface onthe insulating layer for deposition, magnetic members defining amagnetic field in the enclosure, a first source of an alternatingvoltage for providing a first electrical field of a high magnitude inthe enclosure, a first electrode forming a part of the enclosure andconnected to the first source of voltage for providing a negative DCvoltage of a relatively high magnitude at a first position in theenclosure, a second source of an alternating voltage for providing asecond electrical field of a low magnitude in the enclosure, a secondelectrode forming a part of the enclosure and connected to the secondsource of the alternating voltage for providing a negative DC voltage ofa relatively low magnitude at a second position displaced from the firstposition and the wafer but near the first wafer, a conduit forintroducing molecules of an inert gas into the enclosure for ionizationby the combination of the electrical and magnetic fields to produce ionsof high density, the second electrode and the wafer providing a firstcapacitor of a high impedance, and the wafer and the ions in theenclosure providing a second capacitor of a low impedance in a circuitto produce a current of a low magnitude for etching the surface of theinsulating layer in the wafer.
 15. In a combination as set forth inclaim 14, the first capacitor providing a dielectric of the moleculesand ions of the inert gas and the second capacitor providing adielectric constituting the insulating layer.
 16. In a combination asset forth in claim 14, a first electrically conductive member disposedin adjacent relationship to the first electrode and having a referencepotential to provide an electrical field between the first electrode andthe first electrically conductive member, and a second electricallyconductive member disposed in adjacent relationship to the secondelectrode and having the reference potential to provide an electricalfield between the second electrode and the second electricallyconductive member.
 17. In a combination as set forth in claim 14, thewafer having a floating potential and being disposed between the firstand second electrodes in closer proximity to the second electrode thanto the first electrode and being substantially parallel to the first andsecond electrodes.
 18. In a combination as set forth in claim 17, theconduit being disposed adjacent the first electrode to introduce themolecules of the inert gas into the enclosure and the molecules and ionsof the inert gas being passed from the enclosure at a position adjacentto the second electrode.
 19. In a combination as set forth in claim 14,the magnetic members being disposed in a direction substantiallyperpendicular to the first and second electrodes to produce a helicalmovement of electrons in the enclosure and to provide for the productionof the ions from the molecules of the inert gas by the helical movementof the electrons.
 20. In a combination as set forth in claim 13, a firstelectrically conductive member disposed in adjacent relationship to thefirst electrode and having a reference potential to provide anelectrical field between the first electrode and the first electricallyconductive member, a second electrically conductive member disposed inadjacent relationship to the second electrode and having the referencepotential to provide an electrical field between the second electrodeand the second electrically conductive member, the wafer having afloating potential and being disposed between the first and secondelectrodes in closer proximity to the second electrode than to the firstelectrode and being substantially parallel to the first and secondelectrodes, the conduit being disposed adjacent the first electrode tointroduce the molecules of the inert gas into the enclosure and themolecules and ions of the inert gas being passed from the enclosure at aposition adjacent to the second electrode, the magnetic members beingdisposed in a direction substantially perpendicular to the first andsecond electrodes to produce a helical movement of electrons in theenclosure and to provide for the production of the ions from themolecules of the inert gas by the helical movement of the electrons. 21.In combination for etching an insulating layer in a wafer to presentclean and fresh surfaces on the insulating layer for deposition, anenclosure defined by first and second electrodes displaced from eachother and from the wafer for producing electrical fields in theenclosure and further defined by magnetic members for producing amagnetic field in the enclosure, a first voltage source for producing avoltage of a high magnitude on the first electrode to obtain aproduction of a high electrical field in the enclosure, a second voltagesource for producing a voltage of a low magnitude on the secondelectrode to obtain a production of a low electrical field in theenclosure, and a supply of molecules of an inert gas for introductioninto the enclosure to obtain an ionization of the gas molecules in theenclosure by the electrical and magnetic fields in the enclosure and toobtain a movement of the ions in the enclosure to the insulating layerin the wafer at a speed to obtain a smooth and even etching of thesurface of the insulating layer at a low rate without any pits in thesurface of the insulating layer.
 22. A method of etching an insulatinglayer in a wafer to present a clean and fresh surface on the insulationlayer for a deposition on the insulating layer, including the steps of:providing a relatively strong electrical field at first positions in anenclosure, providing a relatively weak electrical field at secondpositions displaced in the enclosure from the first positions, therelatively weak electrical fields defining a capacitor with a highimpedance to limit the transfer of electrical charges to the insulatinglayer in the wafer, passing molecules of an inert gas through theenclosure, and providing a magnetic field in the enclosure in adirection relative to the strong electrical field to obtain a movementof electrons in the enclosure at the positions of the strong electricalfield and an ionization of molecules of the inert gas by the electronsand a movement of the ions in a direction relative to the weakelectrical field to obtain a movement of the ions, in accordance withthe high impedance of the capacitor defined by the relatively weakfield, to the second electrode at a speed for etching the surface of theinsulating layer on the wafer substantially uniformly without pittingthe insulating layer.
 23. A method as set forth in claim 22 wherein therelatively strong electrical field is provided in a first direction andthe relatively weak electrical field is provided in a second directionopposite to the first direction and wherein the magnetic field isprovided in a direction transverse to the first and second directions toproduce a movement of the electrons in the enclosure in a helical pathfor facilitating the ionization of molecules of the inert gas in theenclosure.
 24. A method as set forth in claim 22 the wafer is disposedin the weak electrical field and wherein the molecules of the inert gasare passed through the enclosure initially to positions in the strongelectrical field to obtain an ionization of molecules of the inert gasand subsequently through the enclosure to positions in the weakelectrical field to facilitate an etching of the surface of theinsulating layer on the wafer by the ions.
 25. A method as set forth inclaim 22 wherein the wafer is disposed in the relatively weak electricalfield and wherein an electrode providing the relatively weak field isspaced from, but disposed relatively close to, the wafer to cooperatewith the wafer in providing a high impedance in the capacitor and acircuit including the capacitor for attracting the ions in the weakelectrical field to the wafer to etch the surface of the insulatinglayer on the wafer without pitting the insulating layer.
 26. A method asset forth in claim 21 wherein the capacitor constitutes a firstcapacitor and wherein the relatively weak electrical field is defined bythe first capacitor and a second capacitor in a series circuit andwherein the first capacitor is defined by plates constituting anelectrode and the wafer and in which the plates are separated by a spacein which molecules and ions of the inert gas are disposed to define theinsulator for the capacitor and to provide the first capacitor with thehigh impedance and wherein a second capacitor is defined by platesconstituting the wafer and the ions of the inert gas in the enclosureand wherein the plates are separated by the insulating layer in thewafer to define the insulator of the second capacitor and to provide thesecond capacitor with a relatively low impedance in comparison to thehigh impedance of the first capacitor.
 27. A method as set forth inclaim 26 wherein the relatively strong electrical field is provided by afirst electrode and a first alternating voltage providing a relativelyhigh negative bias on the first electrode and wherein the relativelyweak electrical field is provided by a second electrode and by a secondalternating voltage providing a relatively low bias on the secondelectrode.
 28. A method as set forth in claim 26 wherein the wafer isdisposed in the weak electrical field and wherein the molecules of theinert gas are passed through the enclosure initially through positionsin the strong electrical field to obtain an ionization of molecules ofthe inert gas and subsequently through positions in the weak electricalfield to facilitate an etching of the surface of the insulating layer onthe wafer by the ions and wherein the wafer is disposed in therelatively weak electrical field and wherein an electrode providing therelatively weak field is spaced from, but disposed relatively close to,the wafer to cooperate with the wafer in providing a high impedance inthe capacitor and a circuit including the capacitor for attracting theions in the weak electrical field to the wafer to etch the surface ofthe insulating layer on the wafer without pitting the insulating layer.29. A method as set forth in claim 26 wherein the capacitor constitutesa first capacitor and wherein the first capacitor and a second capacitorare in series and wherein the first capacitor is defined by platesconstituting an electrode and the wafer and in which the plates areseparated by a space in which molecules and ions of the inert gas aredisposed to define the insulator for the capacitor and to provide thehigh impedance and wherein the second capacitor is defined by platesconstituting the wafer and the ions of the inert gas in the enclosureand wherein the plates are separated by the insulating layer in thewafer to define the insulator of the second capacitors and to provide arelatively low impedance in comparison to the high impedance of thefirst capacitor and wherein the relatively strong electrical field isprovided by a first electrode and a first alternating voltage providinga relatively high negative bias on the first electrode and wherein therelatively weak electrical field is provided by a second electrode andby a second alternating voltage providing a relatively low bias on thesecond electrode.
 30. A method of etching an insulating layer on a waferto present a clean and fresh surface on the insulating layer fordeposition, including the steps of passing molecules of an inert gasthrough an enclosure, disposing a first electrode in the enclosure toprovide a strong electrical field in a first direction at firstpositions in the enclosure to ionize molecules of the inert gas in theenclosure, disposing a second electrode in the enclosure to provide aweak electrical field at second positions in the enclosure in a seconddirection opposite to the first direction, providing a magnetic field inthe enclosure, in a direction transverse to the first and seconddirections, to cooperate with the strong electrical field in producingcharged particles in the enclosure and to cooperate with the weakelectrical field in producing a transfer of the charged particles to thesurface of the insulating layer in the wafer to provide a weak andcontrolled etching of the surface of the insulating layer withoutproducing pits in the surface of the insulating layer.
 31. A method asset forth in claim 30 wherein the molecules of the inert gas passthrough the enclosure from the strong electrical field to the weakelectrical field and wherein the magnetic field is substantiallyperpendicular to the first and second electrical fields.
 32. In acombination in claim 30 wherein the strong electrical field is definedin part by the first electrode and by an alternating voltage applied ata first magnitude to the first electrode to bias the first electrode ata negative DC potential with a first magnitude and wherein the weakelectrical field is defined in part by the second electrode and by analternating voltage applied to the second electrode at a secondmagnitude less than the first magnitude to bias the second electrode ata negative DC potential with a second magnitude less than the firstmagnitude for producing the transfer of the charged particles to thesurface of the wafer to provide the weak and controlled etching of thesurface of the insulating layer without producing pits in the surface ofthe insulating layer.
 33. In a combination as set forth in claim 30wherein the magnetic field is provided by magnetic members and whereinthe magnetic members and the first and second electrodes define theenclosure.
 34. In a combination as set forth in claim 30 wherein thewafer is disposed in the weak electrical field and is separated from thesecond electrode in the weak electrical field.
 35. In a combination asset forth in claim 30 wherein the magnetic field is substantiallyperpendicular to the strong and weak electrical fields and wherein themolecules of the inert gas pass into the enclosure through the strongmagnetic field and the molecules and the ions of the inert gas pass fromthe enclosure through the weak electrical field.
 36. A method as setforth in claim 30 wherein the second electrode and the wafer constituteplates of a first capacitor and ions and molecules of the inert gasconstitute the dielectric of the first capacitor and wherein the waferand the ions of the inert gas constitutes plates of a second capacitorand wherein the insulating layer of the wafer constitute the dielectricof the second capacitor and wherein the first capacitor has a higherimpedance than the second capacitor.
 37. A method of etching aninsulating layer on a wafer having at least one socket, defined by wallsin the insulating layer, to present a clean and fresh surface on theinsulating layer, including the walls of the socket, for deposition,including the steps of: passing molecules of an inert gas through anenclosure, providing a strong electrical field at first positions in theenclosure to ionize molecules of the inert gas in the enclosureproviding a weak electrical field at second positions, including thepositions of the wafer, in the enclosure, and providing a magnetic fieldin the enclosure in a direction transverse to the directions of thefirst and second electrical fields in the enclosure to cooperate withthe strong electrical field in producing charged particles and tocooperate with the weak electrical field in producing a transfer of thecharged particles to the surface of the insulating layer in the waferand the walls of the socket in the insulating layer at a low speed toprovide a weak and controlled etching of a uniform thickness from thesurface of the insulating layer and the walls of the socket withoutpitting the surface of the insulating layers or the walls of the socket.38. A method as set forth in claim 37, including the steps of: providinga first electrode in the enclosure for the strong electrical field andintroducing an alternating voltage of a first particular amplitude tothe first electrode to produce a strong negative DC bias on the firstelectrode for the creation of the strong electrical field, providing asecond electrode in the enclosure for the weak electrical field andintroducing an alternating voltage of a second particular amplitude lessthan the first particular amplitude to the second electrode to produce aweak negative DC bias on the second electrode for the creation of theweak electrical field.
 39. A method as set forth in claim 37, includingthe steps of: disposing the wafer in the enclosure in a spacedrelationship to the second electrode to provide a high impedance betweenthe second electrode and the wafer for limiting the transfer of chargedparticles to the surface of the insulating layer and the walls of thesocket and for providing for an elimination of a substantially uniformthickness from the surface of the insulating layer and from the surfacesof the walls of the socket.
 40. A method as set forth in claim 37,including the steps of: providing a first electrode to create the strongelectrical field, providing a second electrode to create the weakelectrical field, providing magnets to create the magnetic field, thefirst and second electrodes and the magnets substantially defining theenclosure, and disposing the wafer in the enclosure in closely spacedrelationship to the second electrode.
 41. A method as set forth in claim37 wherein the wafer is at a floating potential and wherein the magnetsare substantially at a ground potential and wherein first and secondmembers substantially at ground potential are provided respectively inproximity to the first and second electrodes to cooperate respectivelywith the first and second electrodes in creating the strong and weakelectrical fields.
 42. A method as set forth in claim 37 including thesteps of: introducing an alternating voltage of a first particularmagnitude to the first electrode to produce a strong negative DC bias onthe first electrode for the creation of the strong electrical field,introducing an alternating voltage of a second particular magnitude lessthan the first particular magnitude to the second electrode to produce aweak negative bias on the second electrode for the creation of the weakelectrical field, and providing a high impedance between the secondelectrode and the wafer and a low impedance between the wafer and thecharged particles near the wafer to produce a transfer of chargedparticles with limited energy to the surface of the insulating layer andthe walls of the socket in the insulating layer and to provide the weakand controlled etching of the surface of the insulating layer and thewalls of the socket with a uniform thickness of material from theinsulating layer and the wall of the socket without pitting the surfaceof the insulating layer or the walls of the socket.